Reducing Processor Cycle Time Through Partitioning

The multicluster architecture that we introduce o ers a decentralized, dynamically-scheduled architecture, in which the register les, dispatch queue, and functional units of the architecture are distributed across multiple clusters, and each cluster is assigned a subset of the architectural registers. The motivation for the multicluster architecture is to reduce the clock cycle time, relative to a single-cluster architecture with the same number of hardware resources, by reducing the size and complexity of components on critical timing paths. Resource partitioning, however, introduces instruction-execution overhead and may reduce the number of concurrently executing instructions. To counter these two negative by-products of partitioning, we developed a static instruction scheduling algorithm. We describe this algorithm, and using trace-driven simulations of SPEC92 benchmarks, evaluate its e ectiveness. This evaluation indicates that for the con gurations considered, the multicluster architecture may have signi cant performance advantages at feature sizes below 0.35 m, and warrants further investigation. This report is a superset of The Multicluster Architecture: Reducing Cycle Time Through Partitioning, published in the proceedings of The 30th Annual IEEE/ACM Symposium on Microarchitecture, December 1997. A version of this report has also been published in the International Journal of Parallel Programming, 27(5), October 1999.